Method and composite for decreasing charge leakage

ABSTRACT

A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

[0001] This application is a Divisional of U.S. application Ser. No.09/233,313, filed Jan. 19, 1999 which is incorporated herein byreference.

FIELD OF THE INVENTION

[0002] This invention relates to the field of semiconductor memories,and more particularly to a method and manufacture for decreasing chargeleakage in a non-volatile semiconductor memory.

BACKGROUND OF THE INVENTION

[0003] The demand for inexpensive, easily accessible and compact longterm information storage systems continues to increase. In the past, thedemand for long term information storage was met by archiving paperrecords. Today, however, the volume of information requiring storagemakes this solution impractical. Recently, the demand for long terminformation storage has been met by magnetic media information storagesystems and optical information storage systems. Although these systemshave excellent long term information retention capability, in someapplications they are not sufficiently compact. So, a current trend isto use non-volatile semiconductor memory for long term informationstorage.

[0004] Non-volatile semiconductor memory is compact and permits rapidaccess to the stored information. Information is stored in anon-volatile semiconductor memory as electronic charge. The magnitude ofthe electronic charge is used to represent a binary value. For instance,in some memory systems the presence of charge represents a binary one,and the absence of charge represents a binary zero. In other memorysystems, a larger charge magnitude represents a binary one, and asmaller charge magnitude represents a binary zero. In either system,charge isolation is critical to successful long term informationstorage.

[0005] Charge isolation implies that once an electronic charge islocated in a structure, the charge remains at that locationindefinitely. In the art, charge is located in a structure such as atransistor having a control gate, a floating gate, a drain, a source,and a dielectric composite insulator interposed between the control gateand the floating gate. In operation, the control gate induces anelectronic charge to locate at the floating gate. Once the charge isinduced at the floating gate, for the transistor device to successfullyoperate as a long term information storage device, the charge mustremain at the floating gate for a long period of time. As devices arescaled to create higher density memory, the thickness of the dielectricis reduced to maintain the same coupling. As the thickness is reduced,the ability to prevent electron migration through the insulator becomesdifficult. The rate of this charge leakage defines the time that anon-volatile semiconductor memory can function as a long terminformation storage device.

[0006] To successfully substitute for magnetic or optical storagedevices as a long term information storage device, a non-volatilesemiconductor memory device, such as an EPROM, EEPROM, or a flash EPROM,must store information reliably for at least ten years, so any chargeleakage from the floating gate is detrimental to the use of nonvolatilesemiconductor memory as a long term information storage device.

[0007] For these and other reasons there is a need for the presentinvention.

SUMMARY OF THE INVENTION

[0008] The above mentioned problems with charge leakage in memory cellsand other problems are addressed by the present invention and will beunderstood by reading and studying the following specification. A methodand composite for decreasing charge leakage is described.

[0009] The dielectric composite insulator of the present invention, byreducing the charge leakage from the floating gate to the control gateof a memory cell, provides for an improved non-volatile semiconductormemory cell. Reducing the charge leakage in a non-volatile semiconductormemory makes the memory a more viable long term information storagedevice.

[0010] A non-volatile semiconductor memory cell includes a semiconductorsubstrate, a source and drain formed on the semiconductor substrate, aninsulator formed on the source and drain, a floating gate formed on theinsulator, a composite formed on the floating gate and a control gateformed on the composite.

[0011] In one embodiment of the present invention, a layer of undopedpolysilicon, amorphous silicon, or amorphous polysilicon is locatedbetween the floating gate and the layer of silicon dioxide. In analternate embodiment of the present invention, a layer of silicon richnitride is deposited on the layer of silicon nitride and then oxidizedto form the silicon dioxide layer. In still another embodiment of thepresent invention, a layer of undoped polysilicon, amorphous silicon, oramorphous polysilicon is located between the floating gate and thesilicon dioxide, and a layer of silicon rich nitride is located betweenthe layer of silicon nitride and the silicon dioxide of the composite.The effect of interposing a layer of undoped polysilicon, amorphoussilicon, or amorphous polysilicon, which in some designs is thin, or alayer of silicon rich nitride, which in some designs is thin, or bothinto the composite is to decrease the charge leakage from the floatinggate to the control gate of the memory cell. A thin layer of undopedpolysilicon, amorphous silicon, or amorphous polysilicon is a layerhaving a thickness of less than about one-hundred angstroms, and a thinlayer of silicon rich nitride is a layer having a thickness of less thanabout one-hundred angstroms.

[0012] Another embodiment of the present invention also includes aprocess for forming the dielectric insulating composite. In the art, theprocess for forming the composite comprises depositing a layer ofsilicon dioxide on the floating gate, depositing a layer of siliconnitride on the layer of silicon dioxide, and depositing a layer ofsilicon dioxide on the layer of silicon nitride. In the presentinvention, the process for forming the dielectric insulating compositecomprises, in addition to the steps of the process for forming thecomposite, the steps of either depositing a layer of undopedpolysilicon, amorphous silicon, or amorphous polysilicon or depositing alayer of silicon rich nitride, or both. In addition, in one embodimentof the process, after forming the floating gate by flowing silane andphosphine, the deposition of the layer of undoped polysilicon, amorphoussilicon, or amorphous polysilicon is accomplished by reducing the flowof phosphine. In an alternate embodiment of the process, afterdepositing a layer of silicon nitride formed on the layer of silicondioxide by flowing dichlorosilane and ammonia, the deposition of thesilicon rich nitride layer is accomplished by reducing the flow ofammonia. And in still another embodiment, after depositing the layer ofsilicon nitride formed on the layer of silicon dioxide by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block diagram of a composite incorporated in a priorart memory cell.

[0014]FIG. 2 is a block diagram of one embodiment of the composite ofthe present invention incorporated in a memory cell showing a layer ofundoped polysilicon, amorphous silicon, or amorphous polysilicon addedto the prior art memory cell.

[0015]FIG. 3 is a block diagram of a second embodiment of the compositeof the present invention incorporated in a memory cell showing a layerof silicon rich nitride added to the prior art memory cell.

[0016]FIG. 4 is a block diagram of a third embodiment of the compositeof the present invention incorporated in a memory cell showing a layerof undoped polysilicon, amorphous silicon, or amorphous polysilicon anda layer of silicon rich nitride added to the prior art memory cell.

[0017]FIG. 5 is a block diagram of a system incorporating an embodimentof present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the invention may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

[0019] In one embodiment of the present invention a composite acts as adielectric in a memory cell of a non-volatile semiconductor memory.Referring to FIG. 1, a block diagram of a prior art memory cell for usein a non-volatile semiconductor memory is shown. The cell is atransistor comprising a semiconductor substrate 100, a source 110, adrain 120, an insulating layer 130, a floating gate 140, a layer ofsilicon dioxide 150, a layer of silicon nitride 160, a second layer ofsilicon dioxide 170, and a control gate 180. Together, the layer ofsilicon dioxide 150, the layer of silicon nitride 160, and the secondlayer of silicon dioxide 170 make up a composite 190 that acts as adielectric and as an insulator between the control gate 180 and thefloating gate 140. The layer of nitride 160 functions as a dielectric,and the silicon dioxide layers, the layer of silicon dioxide 150 and thesecond layer of silicon dioxide 170, function as insulators.

[0020] In operation, a voltage at the control gate 180 induces a chargeat the floating gate 140. The charge represents stored information. Acharge at the floating gate 140 is prevented from migrating or leakinginto the semiconductor substrate 100 by the insulating layer 130.However, as the composite 190 is reduced in thickness, it becomes aleakage path compared to insulating layer 130, and charge leaks from thefloating gate 140 to the control gate 180. This leakage is admittedlysmall, but over time, as charge leaks from the floating gate 140, theinformation stored at the floating gate 140 is lost. It is this leakagethat limits the performance of prior art memory cells.

[0021] The process for forming the prior art composite 190 requirespartially oxidizing the doped polysilicon of the floating gate 140 toform the layer of silicon dioxide 150, depositing a layer of siliconnitride 160 by chemical vapor deposition on the layer of silicon dioxide150, and partially oxidizing the layer of silicon nitride 160, underaggressive oxidation conditions, to form the second layer of silicondioxide 170. Oxidizing the doped polysilicon layer consumes the wholelayer, while partially oxidizing the doped polysilicon layer consumesless than the whole layer. At the completion of this process, the layerof silicon dioxide 150 contains phosphorous from the doped polysilicon,and the second layer of silicon dioxide 170 contains nitrogen from thelayer of silicon nitride 160. The phosphorous and nitrogen areimpurities that cause significant charge leakage through the silicondioxide layers, when compared to the charge leakage exhibited by silicondioxide layers free of phosphorous and nitrogen.

[0022] Referring to FIG. 2, a diagram of one embodiment of a memory cellfor use in a non-volatile semiconductor memory is shown. The cell is atransistor comprising a semiconductor substrate 200, a source 210, adrain 220, an insulating layer 230, a floating gate 240, a layer ofundoped polysilicon, amorphous silicon, or amorphous polysilicon 245, alayer of silicon dioxide 250, a layer of silicon nitride 260, a secondlayer of silicon dioxide 270, and a control gate 280. Together, thelayer of undoped polysilicon, amorphous silicon, or amorphouspolysilicon 245, the layer of silicon dioxide 250, the layer of siliconnitride 260, and the second layer of silicon dioxide 270 make up acomposite 285 that acts as a dielectric and as an insulator between thecontrol gate 280 and the floating gate 240. The layer of nitride 260functions as a dielectric, and the silicon dioxide layers, the layer ofsilicon dioxide 250 and the second layer of silicon dioxide 270,function as insulators. Amorphous polysilicon is part silicon and partpolysilicon.

[0023] A structural difference between the memory cell of FIG. 1 and oneembodiment of the present invention shown in FIG. 2 is an inter-layerinsulator that is relatively free of impurities. In the embodiment ofFIG. 2 a layer of undoped polysilicon, amorphous silicon, or amorphouspolysilicon 245 is interposed between the floating gate 240 and thelayer of silicon dioxide 250. The layer of silicon dioxide 250 isrelatively free of impurities when the impurity level is at least anorder of magnitude less than the impurity level of a silicon dioxidelayer formed on a floating gate.

[0024] The process for forming the composite 285 requires flowing silaneand phosphine to form the floating gate 240 in a chemical vapordeposition chamber. By decreasing the flow of phosphine, a layer ofundoped polysilicon, amorphous silicon, or amorphous polysilicon 245 isformed on the floating gate 240. In one embodiment of the presentinvention, the flow of phosphine is reduced to zero. The rest of theprocess for forming the composite 285 includes oxidizing or partiallyoxidizing the layer of undoped polysilicon, amorphous silicon, oramorphous polysilicon 245 to form the layer of silicon dioxide 250,depositing a layer of silicon nitride 260 by chemical vapor depositionon the layer of silicon dioxide 250, and oxidizing the layer of siliconnitride 260, under aggressive oxidation conditions, to form the secondlayer of silicon dioxide 270. At the completion of this process, thelayer of silicon dioxide 250 is relatively free of phosphorous anddemonstrates a decrease in charge leakage, when compared with the priorart. By decreasing the concentration of phosphorous, the allowed energylevels or traps are decreased in the layer of silicon dioxide 250.Allowed energy levels or traps are a principal cause of charge leakagein the layer of silicon dioxide 250. This process allows adding the newlayer without removing the wafer from the chemical vapor depositionchamber or adding processing steps.

[0025] Referring to FIG. 3, a diagram of an alternate embodiment of amemory cell for use in a non-volatile semiconductor memory is shown. Thecell is a transistor comprising a semiconductor substrate 300, a source310, a drain 320, an insulating layer 330, a floating gate 340, a layerof silicon dioxide 350, a layer of silicon nitride 360, a layer ofsilicon rich nitride 365, a second layer of silicon dioxide 370, and acontrol gate 380. Together, the layer of silicon dioxide 350, the layerof silicon nitride 360, the layer of silicon rich nitride 365, and thesecond layer of silicon dioxide 370 make up a composite 385 that acts asa dielectric and as an insulator between the control gate 380 and thefloating gate 340. The layer of nitride 360 functions as a dielectric,and the silicon dioxide layers, the layer of silicon dioxide 350 and thesecond layer of silicon dioxide 370, function as insulators.

[0026] A structural difference between the memory cell of FIG. 1 and asecond embodiment of the present invention shown in FIG. 3 is aninter-layer insulator that is relatively free of impurities. In theembodiment of FIG. 3 a layer of silicon rich nitride 365 is interposedbetween the layer of silicon nitride 360 and the layer of silicondioxide 370. The layer of silicon dioxide 370 is relatively free ofimpurities when the impurity level is at least an order of magnitudeless than the impurity level of a silicon dioxide layer formed on alayer of silicon nitride.

[0027] The process for forming the composite 385 requires partiallyoxidizing the doped polysilicon of the floating gate 340 to form thelayer of silicon dioxide 350 and depositing a layer of silicon nitride360 by chemical vapor deposition on the layer of silicon dioxide 350. Asthe layer of silicon nitride 360 is formed by flowing dichlorosilane andammonia or tetrachlorosilane and ammonia, the layer of silicon richnitride 365 is formed by reducing the flow of ammonia. In oneembodiment, the flow of ammonia is reduced to zero. After forming thelayer of silicon rich nitride 365, the second layer of silicon dioxide370 is formed by oxidizing the layer of silicon rich nitride 365. At thecompletion of this process, the second layer of silicon dioxide 370 isrelatively free of nitrogen and demonstrates a decrease in chargeleakage, when compared with the prior art. By decreasing theconcentration of nitrogen, the allowed energy levels or traps aredecreased in the second layer of silicon dioxide 370, and the lessaggressive oxidizing conditions are required to achieve the same silicondioxide thickness.

[0028] Referring to FIG. 4, a diagram of still another embodiment of amemory cell for use in a non-volatile semiconductor memory is shown. Thecell is a transistor comprising a semiconductor substrate 400, a source410, a drain 420, an insulating layer 430, a floating gate 440, a layerof undoped polysilicon, amorphous silicon, or amorphous polysilicon 445,a layer of silicon dioxide 450, a layer of silicon nitride 460, a layerof silicon rich nitride 465, a second layer of silicon dioxide 470, anda control gate 480. Together, the layer of undoped polysilicon,amorphous silicon, or amorphous polysilicon 445, the layer of silicondioxide 450, the layer of silicon nitride 460, the layer of silicon richnitride 465, and the second layer of silicon dioxide 470 make up acomposite 485 that acts as a dielectric and as an insulator between thecontrol gate 480 and the floating gate 440. The layer of nitride 460functions as a dielectric, and the silicon dioxide layers, the layer ofsilicon dioxide 450 and the second layer of silicon dioxide 470,function as insulators.

[0029] Referring to FIG. 4, the third embodiment is a combination of thefirst embodiment and the second embodiment. A structural differencebetween the memory cell of FIG. 1 and the memory cell of FIG. 4 is alayer of undoped polysilicon, amorphous silicon, or amorphouspolysilicon 445 interposed between the floating gate 440 and the layerof silicon dioxide 450 and a layer of silicon rich nitride 465interposed between the layer of silicon nitride 460 and the second layerof silicon dioxide 470. The purpose of the layer of undoped polysilicon,amorphous silicon, or amorphous polysilicon 445 and the layer of siliconrich nitride 465 is to decrease the charge leakage between the floatinggate 440 and the control gate 480. As described in the first embodimentand the second embodiment, the layer of silicon dioxide 450 formed onthe layer of undoped polysilicon, amorphous silicon, or amorphouspolysilicon 445 contains less phosphorous than the corresponding layerin the prior art, and the layer of silicon rich nitride 465 formed onthe layer of silicon nitride 460 contains less nitrogen than thecorresponding layer in the prior art. So, the benefit of firstembodiment, reducing charge leakage in the layer of silicon dioxide 450,and the benefit of the second embodiment, reducing charge leakage in thesecond layer of silicon dioxide 470, accrue to the third embodiment.

[0030] The process for forming the composite 485 combines the processesfor forming the first embodiment and the second embodiment. The floatinggate 440 is formed by flowing silane and phosphine. By decreasing theflow of phosphine, a layer of undoped polysilicon, amorphous silicon, oramorphous polysilicon 445 is formed on the floating gate 440. Oxidizingor partially oxidizing the layer of undoped polysilicon, amorphoussilicon, or amorphous polysilicon 445 forms the layer of silicon dioxide450, and the layer of silicon nitride 460 is formed by chemical vapordeposition on the layer of silicon dioxide 450. After the layer ofsilicon nitride 460 is formed by flowing dichlorosilane and ammonia ortetrachlorosilane and ammonia, the layer of silicon rich nitride 465 isformed by reducing the flow of ammonia. After forming the layer ofsilicon rich nitride 465, the second layer of silicon dioxide 470 isformed by oxidizing the layer of silicon rich nitride 465. At thecompletion of this process, the layer of silicon dioxide is relativelyfree of phosphorous and the layer of silicon rich nitride is relativelyfree of nitrogen, when compared with the prior art. The result is acomposite that exhibits low charge leakage, when compared with the priorart.

[0031] Referring to FIG. 5, a block diagram of a system level embodimentof the present invention is shown. System 500 comprises processor 505and memory device 510, which includes memory cells of one or more of thetypes described above in conjunction with FIGS. 2-4. Memory device 510comprises memory array 515, address circuitry 520, and read circuitry530, and is coupled to processor 505 by address bus 535, data bus 540,and control bus 545. Processor 505, through address bus 535, data bus540, and control bus 545 communicates with memory device 510. In a readoperation initiated by processor 505, address information, datainformation, and control information are provided to memory device 510through busses 535, 540, and 545. This information is decoded byaddressing circuitry 520, including a row decoder and a column decoder,and read circuitry 530. Successful completion of the read operationresults in information from memory array 515 being communicated toprocessor 505 over data bus 540.

CONCLUSION

[0032] An embodiment of a nonvolatile memory cell has been describedwhich has a undoped polysilicon, amorphous silicon, or amorphouspolysilicon layer and a silicon rich nitride layer. This embodimentexhibits low charge leakage. A system embodiment of the invention hasalso been described.

[0033] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. A dielectric composite for insulating a floatinggate from a control gate, the composite comprising: a layer of undopedpolysilicon formed on the floating gate; a layer of silicon dioxideformed by oxidizing the layer of undoped polysilicon; a layer of siliconnitride formed on the layer of silicon dioxide; and a second layer ofsilicon dioxide formed on the layer of silicon nitride, the control gateformed on the second layer of silicon dioxide.
 2. The composite of claim1, wherein the layer of silicon dioxide is formed by chemical vapordeposition and the second layer of silicon dioxide is formed byoxidation.
 3. The composite of claim 1, wherein the layer of undopedpolysilicon is thin.
 4. A dielectric composite for insulating a floatinggate from a control gate, the composite comprising: a layer of undopedpolysilicon formed on the floating gate; a layer of silicon dioxideformed by partially oxidizing the layer of undoped polysilicon; a layerof silicon nitride formed on the layer of silicon dioxide; and a secondlayer of silicon dioxide formed on the layer of silicon nitride, thecontrol gate formed on the second layer of silicon dioxide.
 5. Thecomposite of claim 4, wherein the layer of silicon dioxide is formed bychemical vapor deposition and the second layer of silicon dioxide isformed by oxidation.
 6. The composite of claim 4, wherein the layer ofundoped polysilicon is thin.
 7. A dielectric composite for insulating afloating gate from a control gate, the composite comprising: a layer ofsilicon dioxide formed on the floating gate; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the layer of silicon rich nitride, the control gateformed on the second layer of silicon dioxide.
 8. The composite of claim7, wherein the layer of silicon dioxide formed on the floating gate isformed by oxidation and the second layer of silicon dioxide formed onthe layer of silicon nitride is formed by chemical vapor deposition. 9.The composite of claim 7, wherein the layer of silicon rich nitride isthin.
 10. A dielectric composite for insulating a floating gate from acontrol gate, the composite comprising: a layer of undoped polysiliconformed on the floating gate; a layer of silicon dioxide formed byoxidizing the layer of undoped polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the layer of silicon rich nitride, the control gateformed on the second layer of silicon dioxide.
 11. The composite ofclaim 10, wherein the layer of silicon dioxide and the second layer ofsilicon dioxide are formed by chemical vapor deposition.
 12. Thecomposite of claim 10, wherein the layer of undoped polysilicon and thelayer of silicon rich nitride are thin.
 13. A dielectric composite forinsulating a floating gate from a control gate, the compositecomprising: a layer of undoped polysilicon formed on the floating gate;a layer of silicon dioxide formed by partially oxidizing the layer ofundoped polysilicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; a layer of silicon rich nitride formed on the layer ofsilicon nitride; and a second layer of silicon dioxide formed on thelayer of silicon rich nitride, the control gate formed on the secondlayer of silicon dioxide.
 14. The composite of claim 13, wherein thelayer of silicon dioxide and the second layer of silicon dioxide areformed by chemical vapor deposition.
 15. The composite of claim 13,wherein the layer of undoped polysilicon and the layer of silicon richnitride are thin.
 16. A process for forming a dielectric composite forinsulating a floating gate from a control gate, the process comprising:depositing a layer of undoped polysilicon on the floating gate; forminga layer of silicon dioxide by oxidizing the layer of undopedpolysilicon; depositing a layer of silicon nitride on the layer ofsilicon dioxide; and forming a second layer of silicon dioxide byoxidizing the layer of silicon nitride, the control gate formed on thesecond layer of silicon dioxide.
 17. The process of claim 16, whereindepositing a layer of undoped polysilicon results in a thin layer ofundoped polysilicon.
 18. The process of claim 16, wherein after formingthe floating gate by flowing silane and phosphine, the deposition of thelayer of undoped polysilicon is accomplished by reducing the flow ofphosphine.
 19. The process of claim 18, wherein the flow of phosphine isreduced to zero.
 20. A process for forming a dielectric composite forinsulating a floating gate from a control gate, the process comprising:depositing a layer of undoped polysilicon on the floating gate; forminga layer of silicon dioxide by partially oxidizing the layer of undopedpolysilicon; depositing a layer of silicon nitride on the layer ofsilicon dioxide; and forming a second layer of silicon dioxide byoxidizing the layer of silicon nitride, the control gate formed on thesecond layer of silicon dioxide.
 21. The process of claim 20, whereindepositing a layer of undoped polysilicon results in a thin layer ofundoped polysilicon.
 22. The process of claim 20, wherein after formingthe floating gate by flowing silane and phosphine, the deposition of thelayer of undoped polysilicon is accomplished by reducing the flow ofphosphine.
 23. The process of claim 22, wherein the flow of phosphine isreduced to zero.
 24. A process for forming a dielectric composite forinsulating a floating gate from a control gate, the process comprising:forming a layer of silicon dioxide by partially oxidizing the floatinggate; depositing a layer of silicon nitride on the layer of silicondioxide; depositing a layer of silicon rich nitride on the layer ofsilicon nitride; and forming a second layer of silicon dioxide byoxidizing the layer of silicon rich nitride, the control gate formed onthe second layer of silicon dioxide.
 25. The process of claim 24,wherein depositing a layer of silicon rich nitride results in a thinlayer of silicon rich nitride.
 26. The process of claim 24, whereinafter depositing a layer of silicon nitride formed on the layer ofsilicon dioxide by flowing dichlorosilane and ammonia, the deposition ofthe silicon rich nitride layer is accomplished by reducing the flow ofammonia.
 27. The process of claim 26, wherein, the flow of ammonia isreduced to zero.
 28. The process of claim 24, wherein after depositing alayer of silicon nitride formed on the layer of silicon dioxide byflowing tetrachlorosilane and ammonia, the deposition of the siliconrich nitride layer is accomplished by reducing the flow of ammonia. 29.The process of claim 28, wherein the flow of ammonia is reduced to zero.30. A process for forming a dielectric composite for insulating afloating gate from a control gate, the process comprising: depositing alayer of undoped polysilicon on the floating gate; forming a layer ofsilicon dioxide by oxidizing the layer of undoped polysilicon;depositing a layer of silicon nitride on the layer of silicon dioxide;depositing a layer of silicon rich nitride on the layer of siliconnitride; and forming a second layer of silicon dioxide by oxidizing thelayer of silicon rich nitride, the control gate formed on the secondlayer of silicon dioxide.
 31. The process of claim 30, whereindepositing of the layer of undoped polysilicon results in a thin layerof undoped polysilicon, and depositing a layer of silicon rich nitrideresults in a thin layer of silicon rich nitride.
 32. The process ofclaim 30, wherein after forming the floating gate by flowing silane andphosphine, the deposition of the layer of undoped polysilicon isaccomplished by reducing the flow of phosphine.
 33. The process of claim31, wherein the flow of phosphine is reduced to zero.
 34. The process ofclaim 30, wherein after depositing a layer of silicon nitride by flowingdichlorosilane and ammonia, the deposition of the layer of silicon richnitride is accomplished by reducing the flow of ammonia.
 35. The processof claim 34, wherein the flow of ammonia is reduced to zero.
 36. Theprocess of claim 30, wherein after forming the floating gate by flowingsilane and phosphine, the deposition of the layer of undoped polysiliconis accomplished by reducing the flow of phosphine, and after depositingthe layer of silicon nitride by flowing dichlorosilane and ammonia, thedeposition of the silicon rich nitride layer is accomplished by reducingthe flow of ammonia.
 37. The process of claim 36, wherein the flow ofphosphine is reduced to zero, and the flow of ammonia is reduced tozero.
 38. The process of claim 30, wherein after depositing a layer ofsilicon nitride by flowing tetrachlorosilane and ammonia, the depositionof the silicon rich nitride layer is accomplished by reducing the flowof ammonia.
 39. The process of claim 38, wherein the flow of ammonia isreduced to zero.
 40. The process of claim 30, wherein after forming thefloating gate by flowing silane and phosphine, the deposition of thelayer of undoped polysilicon is accomplished by reducing the flow ofphosphine, and after depositing the layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 41. Theprocess of claim 40, wherein the flow of phosphine is reduced to zero,and the flow of ammonia is reduced to zero.
 42. A nonvolatile memorycell comprising: a substrate; a source and drain formed on thesubstrate; an insulator formed on the source and drain; a floating gateformed on the insulator; a composite formed on the floating gate, thecomposite comprising: a layer of undoped polysilicon formed on thefloating gate; a layer of silicon dioxide formed on the layer of undopedpolysilicon; a layer of silicon nitride formed on the layer of silicondioxide; and a second layer of silicon dioxide formed on the siliconrich nitride; and a control gate formed on the composite.
 43. Thenonvolatile memory cell of claim 42, wherein the insulator is a tunneloxide.
 44. The nonvolatile memory cell of claim 42, wherein the layer ofundoped polysilicon formed on the floating gate is thin.
 45. Anonvolatile memory cell comprising: a substrate; a source and drainformed on the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of silicon dioxideformed on the floating gate; a layer of silicon nitride formed on thelayer of silicon dioxide; a layer of silicon rich nitride formed on thelayer of silicon nitride; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite.46. The nonvolatile memory cell of claim 45, wherein the insulator is atunnel oxide.
 47. The nonvolatile memory cell of claim 45, wherein thelayer of silicon rich nitride formed on the layer of silicon nitride isthin.
 48. A nonvolatile memory cell comprising: a substrate; a sourceand drain formed on the substrate; an insulator formed on the source anddrain; a floating gate formed on the insulator; a composite formed onthe floating gate, the composite comprising: a layer of undopedpolysilicon formed on the floating gate; a layer of silicon dioxideformed on the layer of undoped polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the silicon rich nitride; and a control gate formed onthe composite.
 49. The nonvolatile memory cell of claim 48, wherein theinsulator is a tunnel oxide.
 50. The nonvolatile memory cell of claim48, wherein the layer of undoped polysilicon formed on the floating gateis thin.
 51. The nonvolatile memory cell of claim 48, wherein the layerof silicon rich nitride formed on the layer of silicon nitride is thin.52. The nonvolatile memory cell of claim 48, wherein the layer ofundoped polysilicon formed on the floating gate is thin and the layer ofsilicon rich nitride formed on the layer of silicon nitride is thin. 53.A memory device, comprising: a plurality of memory cells, at least oneof the memory cells comprising: a substrate; a source and drain formedon the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of undoped polysiliconformed on the floating gate; a layer of silicon dioxide formed on thelayer of undoped polysilicon; a layer of silicon nitride formed on thelayer of silicon dioxide; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite;addressing circuity coupled to the plurality of memory cells foraccessing at least one of the memory cells; and a read circuit coupledto the plurality of memory cells for reading data from at least one ofthe memory cells.
 54. The memory device of claim 53, wherein theinsulator is a tunnel oxide.
 55. The memory device of claim 53, whereinthe layer of undoped polysilicon formed on the floating gate is thin.56. A memory device, comprising: a plurality of memory cells, at leastone of the memory cells comprising: a substrate; a source and drainformed on the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of silicon dioxideformed on the floating gate; a layer of silicon nitride formed on thelayer of silicon dioxide; a layer of silicon rich nitride formed on thelayer of silicon nitride; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite;addressing circuity coupled to the plurality of memory cells foraccessing at least one of the memory cells; and a read circuit coupledto the plurality of memory cells for reading data from at least one ofthe memory cells.
 57. The memory device of claim 56, wherein theinsulator is a tunnel oxide.
 58. The memory device of claim 56, whereinthe layer of silicon rich nitride formed on the layer of silicon nitrideis thin.
 59. A memory device, comprising: a plurality of memory cells,at least one of the memory cells comprising: a substrate; a source anddrain formed on the substrate; an insulator formed on the source anddrain; a floating gate formed on the insulator; a composite formed onthe floating gate, the composite comprising: a layer of undopedpolysilicon formed on the floating gate; a layer of silicon dioxideformed on the layer of undoped polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the silicon rich nitride; and a control gate formed onthe composite; addressing circuity coupled to the plurality of memorycells for accessing at least one of the memory cells; and a read circuitcoupled to the plurality of memory cells for reading data from at leastone of the memory cells.
 60. The memory device of claim 59, wherein theinsulator is a tunnel oxide.
 61. The memory device of claim 59, whereinthe layer of undoped polysilicon formed on the floating gate is thin.62. The memory device of claim 59, wherein the layer of silicon richnitride formed on the layer of silicon nitride is thin.
 63. The memorydevice of claim 59, wherein the layer of undoped polysilicon formed onthe floating gate is thin and the layer of silicon rich nitride formedon the layer of silicon nitride is thin.
 64. A system comprising: aprocessor; and a memory device coupled to the processor, the memorydevice comprising: a plurality of memory cells, at least one of thememory cells comprising: a substrate; a source and drain formed on thesubstrate; an insulator formed on the source and drain; a floating gateformed on the insulator; a composite formed on the floating gate, thecomposite comprising: a layer of undoped polysilicon formed on thefloating gate; a layer of silicon dioxide formed on the layer of undopedpolysilicon; a layer of silicon nitride formed on the layer of silicondioxide; and a second layer of silicon dioxide formed on the siliconrich nitride; and a control gate formed on the composite; addressingcircuity coupled to the plurality of memory cells for accessing at leastone of the memory cells; and a read circuit coupled to the plurality ofmemory cells for reading data from at least one of the memory cells. 65.The system of claim 64, wherein the insulator is a tunnel oxide.
 66. Thesystem of claim 64, wherein the layer of undoped polysilicon formed onthe floating gate is thin.
 67. A system comprising: a processor; and amemory device coupled to the processor, the memory device comprising: aplurality of memory cells, at least one of the memory cells comprising:a substrate; a source and drain formed on the substrate; an insulatorformed on the source and drain; a floating gate formed on the insulator;a composite formed on the floating gate, the composite comprising: alayer of silicon dioxide formed on the floating gate; a layer of siliconnitride formed on the layer of silicon dioxide; a layer of silicon richnitride formed on the layer of silicon nitride; and a second layer ofsilicon dioxide formed on the silicon rich nitride; and a control gateformed on the composite; addressing circuity coupled to the plurality ofmemory cells for accessing at least one of the memory cells; and a readcircuit coupled to the plurality of memory cells for reading data fromat least one of the memory cells.
 68. The system of claim 67, whereinthe insulator is a tunnel oxide.
 69. The system of claim 67, wherein thelayer of silicon rich nitride formed on the layer of silicon nitride isthin.
 70. A system comprising: a processor; and a memory device coupledto the processor, the memory device comprising: a plurality of memorycells, at least one of the memory cells comprising: a substrate; asource and drain formed on the substrate; an insulator formed on thesource and drain; a floating gate formed on the insulator; a compositeformed on the floating gate, the composite comprising: a layer ofundoped polysilicon formed on the floating gate; a layer of silicondioxide formed on the layer of undoped polysilicon; a layer of siliconnitride formed on the layer of silicon dioxide; a layer of silicon richnitride formed on the layer of silicon nitride; and a second layer ofsilicon dioxide formed on the silicon rich nitride; and a control gateformed on the composite; addressing circuity coupled to the plurality ofmemory cells for accessing at least one of the memory cells; and a readcircuit coupled to the plurality of memory cells for reading data fromat least one of the memory cells.
 71. The system of claim 70, whereinthe insulator is a tunnel oxide.
 72. The system of claim 70, wherein thelayer of undoped polysilicon formed on the floating gate is thin. 73.The system of claim 70, wherein the layer of silicon rich nitride formedon the layer of silicon nitride is thin.
 74. The system of claim 70,wherein the layer of undoped polysilicon formed on the floating gate isthin and the layer of silicon rich nitride formed on the layer ofsilicon nitride is thin.
 75. A nonvolatile memory cell comprising: asubstrate; a source and drain formed on the substrate; an insulatorformed on the source and drain; a floating gate formed on the insulator;a composite formed on the floating gate and having an inter-layerinsulator that is relatively free of impurities; and a control gateformed on the composite.
 76. The non-volatile memory cell of claim 75,wherein the inter-layer insulator is a layer of silicon dioxide.
 77. Thenon-volatile memory cell of claim 75, wherein the inter-layer insulatoris a layer of silicon dioxide formed on a layer of undoped polysilicon.78. The non-volatile memory cell of claim 75, wherein the inter-layerinsulator is a layer of silicon dioxide formed on a layer of amorphoussilicon.
 79. The non-volatile memory cell of claim 75, wherein theinter-layer insulator is a layer of silicon dioxide formed on a layer ofamorphous polysilicon.
 80. The non-volatile memory cell of claim 75,wherein the inter-layer insulator is a layer of silicon dioxide formedon a layer of silicon rich nitride.
 81. A memory device, comprising: anonvolatile memory cell having an inter-layer insulator that isrelatively free of impurities; an addressing circuit coupled to thememory cell for accessing the memory cell; and a read circuit coupled tothe memory cell for reading from the memory cell.
 82. The memory deviceof claim 81, wherein the inter-layer insulator is a layer of silicondioxide.
 83. The memory device of claim 81, wherein the inter-layerinsulator is a layer of silicon dioxide formed on a layer of undopedpolysilicon.
 84. The memory device of claim 81, wherein the inter-layerinsulator is a layer of silicon dioxide formed on a layer of amorphoussilicon.
 85. The memory device of claim 81, wherein the inter-layerinsulator is a layer of silicon dioxide formed on a layer of amorphouspolysilicon.
 86. The memory device of claim 81, wherein the inter-layerinsulator is a layer of silicon dioxide formed on a layer of siliconrich nitride.
 87. A system comprising: a processor; and a memory devicecoupled to the processor, the memory device comprising: a nonvolatilememory cell having an inter-layer insulator that is relatively free ofimpurities; an addressing circuit coupled to the memory cell foraccessing the memory cell; and a read circuit coupled to the memory cellfor reading from the memory cell.
 88. The memory device of claim 87,wherein the inter-layer insulator is a layer of silicon dioxide.
 89. Thememory device of claim 87, wherein the inter-layer insulator is a layerof silicon dioxide formed on a layer of undoped polysilicon.
 90. Thememory device of claim 87, wherein the inter-layer insulator is a layerof silicon dioxide formed on a layer of amorphous silicon.
 91. Thememory device of claim 87, wherein the inter-layer insulator is a layerof silicon dioxide formed on a layer of amorphous polysilicon.
 92. Thememory device of claim 87, wherein the inter-layer insulator is a layerof silicon dioxide formed on a layer of silicon rich nitride.
 93. Atransistor comprising: a substrate; a source and drain formed on thesubstrate; an insulator formed on the source and drain; a floating gateformed on the insulator; a composite formed on the floating gate andhaving an inter-layer insulator that is relatively free of impurities;and a control gate formed on the composite.
 94. The transistor of claim93, wherein the inter-layer insulator is a layer of silicon dioxide. 95.The transistor of claim 93, wherein the inter-layer insulator is a layerof silicon dioxide formed on a layer of undoped polysilicon.
 96. Thetransistor of claim 93, wherein the inter-layer insulator is a layer ofsilicon dioxide formed on a layer of amorphous silicon.
 97. Thetransistor of claim 93, wherein the inter-layer insulator is a layer ofsilicon dioxide formed on a layer of amorphous polysilicon.
 98. Thetransistor of claim 93, wherein the inter-layer insulator is a layer ofsilicon dioxide formed on a layer of silicon rich nitride.
 99. Adielectric composite for insulating a floating gate from a control gate,the composite comprising: a layer of amorphous silicon formed on thefloating gate; a layer of silicon dioxide formed by oxidizing the layerof amorphous silicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; and a second layer of silicon dioxide formed on thelayer of silicon nitride, the control gate formed on the second layer ofsilicon dioxide.
 100. The composite of claim 99, wherein the layer ofsilicon dioxide is formed by chemical vapor deposition and the secondlayer of silicon dioxide is formed by oxidation.
 101. The composite ofclaim 99, wherein the layer of amorphous silicon is thin.
 102. Adielectric composite for insulating a floating gate from a control gate,the composite comprising: a layer of amorphous silicon formed on thefloating gate; a layer of silicon dioxide formed by partially oxidizingthe layer of amorphous silicon; a layer of silicon nitride formed on thelayer of silicon dioxide; and a second layer of silicon dioxide formedon the layer of silicon nitride, the control gate formed on the secondlayer of silicon dioxide.
 103. The composite of claim 102, wherein thelayer of silicon dioxide is formed by chemical vapor deposition and thesecond layer of silicon dioxide is formed by oxidation.
 104. Thecomposite of claim 102, wherein the layer of amorphous silicon is thin.105. A dielectric composite for insulating a floating gate from acontrol gate, the composite comprising: a layer of amorphous siliconformed on the floating gate; a layer of silicon dioxide formed byoxidizing the layer of amorphous silicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the layer of silicon rich nitride, the control gateformed on the second layer of silicon dioxide.
 106. The composite ofclaim 105, wherein the layer of silicon dioxide and the second layer ofsilicon dioxide are formed by chemical vapor deposition.
 107. Thecomposite of claim 105, wherein the layer of amorphous silicon and thelayer of silicon rich nitride are thin.
 108. A dielectric composite forinsulating a floating gate from a control gate, the compositecomprising: a layer of amorphous silicon formed on the floating gate; alayer of silicon dioxide formed by partially oxidizing the layer ofamorphous silicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; a layer of silicon rich nitride formed on the layer ofsilicon nitride; and a second layer of silicon dioxide formed on thelayer of silicon rich nitride, the control gate formed on the secondlayer of silicon dioxide.
 109. The composite of claim 108, wherein thelayer of silicon dioxide and the second layer of silicon dioxide areformed by chemical vapor deposition.
 110. The composite of claim 108,wherein the layer of amorphous silicon and the layer of silicon richnitride are thin.
 111. A process for forming a dielectric composite forinsulating a floating gate from a control gate, the process comprising:depositing a layer of amorphous silicon on the floating gate; forming alayer of silicon dioxide by oxidizing the layer of amorphous silicon;depositing a layer of silicon nitride on the layer of silicon dioxide;and forming a second layer of silicon dioxide by oxidizing the layer ofsilicon nitride, the control gate formed on the second layer of silicondioxide.
 112. The process of claim 111, wherein depositing a layer ofamorphous silicon results in a thin layer of amorphous silicon.
 113. Theprocess of claim 111, wherein after forming the floating gate by flowingsilane and phosphine, the deposition of the layer of amorphous siliconis accomplished by reducing the flow of phosphine.
 114. The process ofclaim 113, wherein the flow of phosphine is reduced to zero.
 115. Aprocess for forming a dielectric composite for insulating a floatinggate from a control gate, the process comprising: depositing a layer ofamorphous silicon on the floating gate; forming a layer of silicondioxide by partially oxidizing the layer of amorphous silicon;depositing a layer of silicon nitride on the layer of silicon dioxide;and forming a second layer of silicon dioxide by oxidizing the layer ofsilicon nitride, the control gate formed on the second layer of silicondioxide.
 116. The process of claim 115, wherein depositing a layer ofamorphous silicon results in a thin layer of amorphous silicon.
 117. Theprocess of claim 115, wherein after forming the floating gate by flowingsilane and phosphine, the deposition of the layer of amorphous siliconis accomplished by reducing the flow of phosphine.
 118. The process ofclaim 117, wherein the flow of phosphine is reduced to zero.
 119. Aprocess for forming a dielectric composite for insulating a floatinggate from a control gate, the process comprising: depositing a layer ofamorphous silicon on the floating gate; forming a layer of silicondioxide by oxidizing the layer of amorphous silicon; depositing a layerof silicon nitride on the layer of silicon dioxide; depositing a layerof silicon rich nitride on the layer of silicon nitride; and forming asecond layer of silicon dioxide by oxidizing the layer of silicon richnitride, the control gate formed on the second layer of silicon dioxide.120. The process of claim 119, wherein depositing of the layer ofamorphous silicon results in a thin layer of amorphous silicon, anddepositing a layer of silicon rich nitride results in a thin layer ofsilicon rich nitride.
 121. The process of claim 119, wherein afterforming the floating gate by flowing silane and phosphine, thedeposition of the layer of amorphous silicon is accomplished by reducingthe flow of phosphine.
 122. The process of claim 120, wherein the flowof phosphine is reduced to zero.
 123. The process of claim 119, whereinafter depositing a layer of silicon nitride by flowing dichlorosilaneand ammonia, the deposition of the layer of silicon rich nitride isaccomplished by reducing the flow of ammonia.
 124. The process of claim123, wherein the flow of ammonia is reduced to zero.
 125. The process ofclaim 119, wherein after forming the floating gate by flowing silane andphosphine, the deposition of the layer of amorphous silicon isaccomplished by reducing the flow of phosphine, and after depositing thelayer of silicon nitride by flowing dichlorosilane and ammonia, thedeposition of the silicon rich nitride layer is accomplished by reducingthe flow of ammonia.
 126. The process of claim 125, wherein the flow ofphosphine is reduced to zero, and the flow of ammonia is reduced tozero.
 127. The process of claim 119, wherein after depositing a layer ofsilicon nitride by flowing tetrachlorosilane and ammonia, the depositionof the silicon rich nitride layer is accomplished by reducing the flowof ammonia.
 128. The process of claim 127, wherein the flow of ammoniais reduced to zero.
 129. The process of claim 119, wherein after formingthe floating gate by flowing silane and phosphine, the deposition of thelayer of amorphous silicon is accomplished by reducing the flow ofphosphine, and after depositing the layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 130. Theprocess of claim 129, wherein the flow of phosphine is reduced to zero,and the flow of ammonia is reduced to zero.
 131. A process for forming adielectric composite for insulating a floating gate from a control gate,the process comprising: depositing a layer of amorphous silicon on thefloating gate; forming a layer of silicon dioxide by partially oxidizingthe layer of amorphous silicon; depositing a layer of silicon nitride onthe layer of silicon dioxide; depositing a layer of silicon rich nitrideon the layer of silicon nitride; and forming a second layer of silicondioxide by oxidizing the layer of silicon rich nitride, the control gateformed on the second layer of silicon dioxide.
 132. The process of claim131, wherein depositing of the layer of amorphous silicon results in athin layer of amorphous silicon, and depositing a layer of silicon richnitride results in a thin layer of silicon rich nitride.
 133. Theprocess of claim 131, wherein after forming the floating gate by flowingsilane and phosphine, the deposition of the layer of amorphous siliconis accomplished by reducing the flow of phosphine.
 134. The process ofclaim 133, wherein the flow of phosphine is reduced to zero.
 135. Theprocess of claim 131, wherein after depositing a layer of siliconnitride by flowing dichlorosilane and ammonia, the deposition of thelayer of silicon rich nitride is accomplished by reducing the flow ofammonia.
 136. The process of claim 135, wherein the flow of ammonia isreduced to zero.
 137. The process of claim 131, wherein after formingthe floating gate by flowing silane and phosphine, the deposition of thelayer of amorphous silicon is accomplished by reducing the flow ofphosphine, and after depositing the layer of silicon nitride by flowingdichlorosilane and ammonia, the deposition of the silicon rich nitridelayer is accomplished by reducing the flow of ammonia.
 138. The processof claim 137, wherein the flow of phosphine is reduced to zero, and theflow of ammonia is reduced to zero.
 139. The process of claim 131,wherein after depositing a layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 140. Theprocess of claim 139, wherein the flow of ammonia is reduced to zero.141. The process of claim 131, wherein after forming the floating gateby flowing silane and phosphine, the deposition of the layer ofamorphous silicon is accomplished by reducing the flow of phosphine, andafter depositing the layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 142. Theprocess of claim 141, wherein the flow of phosphine is reduced to zero,and the flow of ammonia is reduced to zero.
 143. A nonvolatile memorycell comprising: a substrate; a source and drain formed on thesubstrate; an insulator formed on the source and drain; a floating gateformed on the insulator; a composite formed on the floating gate, thecomposite comprising: a layer of amorphous silicon formed on thefloating gate; a layer of silicon dioxide formed on the layer ofamorphous silicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; and a second layer of silicon dioxide formed on thesilicon rich nitride; and a control gate formed on the composite. 144.The nonvolatile memory cell of claim 143, wherein the insulator is atunnel oxide.
 145. The nonvolatile memory cell of claim 143, wherein thelayer of amorphous silicon formed on the floating gate is thin.
 146. Anonvolatile memory cell comprising: a substrate; a source and drainformed on the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of amorphous siliconformed on the floating gate; a layer of silicon dioxide formed on thelayer of amorphous silicon; a layer of silicon nitride formed on thelayer of silicon dioxide; a layer of silicon rich nitride formed on thelayer of silicon nitride; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite.147. The nonvolatile memory cell of claim 146, wherein the insulator isa tunnel oxide.
 148. The nonvolatile memory cell of claim 146, whereinthe layer of amorphous silicon formed on the floating gate is thin. 149.The nonvolatile memory cell of claim 146, wherein the layer of siliconrich nitride formed on the layer of silicon nitride is thin.
 150. Thenonvolatile memory cell of claim 146, wherein the layer of amorphoussilicon formed on the floating gate is thin and the layer of siliconrich nitride formed on the layer of silicon nitride is thin.
 151. Amemory device, comprising: a plurality of memory cells, at least one ofthe memory cells comprising: a substrate; a source and drain formed onthe substrate; an insulator formed on the source and drain; a floatinggate formed on the insulator; a composite formed on the floating gate,the composite comprising: a layer of amorphous silicon formed on thefloating gate; a layer of silicon dioxide formed on the layer ofamorphous silicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; and a second layer of silicon dioxide formed on thesilicon rich nitride; and a control gate formed on the composite;addressing circuity coupled to the plurality of memory cells foraccessing at least one of the memory cells; and a read circuit coupledto the plurality of memory cells for reading data from at least one ofthe memory cells.
 152. The memory device of claim 151, wherein theinsulator is a tunnel oxide.
 153. The memory device of claim 151,wherein the layer of amorphous silicon formed on the floating gate isthin.
 154. A memory device, comprising: a plurality of memory cells, atleast one of the memory cells comprising: a substrate; a source anddrain formed on the substrate; an insulator formed on the source anddrain; a floating gate formed on the insulator; a composite formed onthe floating gate, the composite comprising: a layer of amorphoussilicon formed on the floating gate; a layer of silicon dioxide formedon the layer of amorphous silicon; a layer of silicon nitride formed onthe layer of silicon dioxide; a layer of silicon rich nitride formed onthe layer of silicon nitride; and a second layer of silicon dioxideformed on the silicon rich nitride; and a control gate formed on thecomposite; addressing circuity coupled to the plurality of memory cellsfor accessing at least one of the memory cells; and a read circuitcoupled to the plurality of memory cells for reading data from at leastone of the memory cells.
 155. The memory device of claim 154, whereinthe insulator is a tunnel oxide.
 156. The memory device of claim 154,wherein the layer of amorphous silicon formed on the floating gate isthin.
 157. The memory device of claim 154, wherein the layer of siliconrich nitride formed on the layer of silicon nitride is thin.
 158. Thememory device of claim 154, wherein the layer of amorphous siliconformed on the floating gate is thin and the layer of silicon richnitride formed on the layer of silicon nitride is thin.
 159. A systemcomprising: a processor; and a memory device coupled to the processor,the memory device comprising: a plurality of memory cells, at least oneof the memory cells comprising: a substrate; a source and drain formedon the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of amorphous siliconformed on the floating gate; a layer of silicon dioxide formed on thelayer of amorphous silicon; a layer of silicon nitride formed on thelayer of silicon dioxide; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite;addressing circuity coupled to the plurality of memory cells foraccessing at least one of the memory cells; and a read circuit coupledto the plurality of memory cells for reading data from at least one ofthe memory cells.
 160. The system of claim 159, wherein the insulator isa tunnel oxide.
 161. The system of claim 159, wherein the layer ofamorphous silicon formed on the floating gate is thin.
 162. A systemcomprising: a processor; and a memory device coupled to the processor,the memory device comprising: a plurality of memory cells, at least oneof the memory cells comprising: a substrate; a source and drain formedon the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of amorphous siliconformed on the floating gate; a layer of silicon dioxide formed on thelayer of amorphous silicon; a layer of silicon nitride formed on thelayer of silicon dioxide; a layer of silicon rich nitride formed on thelayer of silicon nitride; and a second layer of silicon dioxide formedon the silicon rich nitride; and a control gate formed on the composite;addressing circuity coupled to the plurality of memory cells foraccessing at least one of the memory cells; and a read circuit coupledto the plurality of memory cells for reading data from at least one ofthe memory cells.
 163. The system of claim 162, wherein the insulator isa tunnel oxide.
 164. The system of claim 162, wherein the layer ofamorphous silicon formed on the floating gate is thin.
 165. The systemof claim 162, wherein the layer of silicon rich nitride formed on thelayer of silicon nitride is thin.
 166. The system of claim 162, whereinthe layer of amorphous silicon formed on the floating gate is thin andthe layer of silicon rich nitride formed on the layer of silicon nitrideis thin.
 167. A dielectric composite for insulating a floating gate froma control gate, the composite comprising: a layer of amorphouspolysilicon formed on the floating gate; a layer of silicon dioxideformed by oxidizing the layer of amorphous polysilicon; a layer ofsilicon nitride formed on the layer of silicon dioxide; and a secondlayer of silicon dioxide formed on the layer of silicon nitride, thecontrol gate formed on the second layer of silicon dioxide.
 168. Thecomposite of claim 167, wherein the layer of silicon dioxide is formedby chemical vapor deposition and the second layer of silicon dioxide isformed by oxidation.
 169. The composite of claim 167, wherein the layerof amorphous polysilicon is thin.
 170. A dielectric composite forinsulating a floating gate from a control gate, the compositecomprising: a layer of amorphous polysilicon formed on the floatinggate; a layer of silicon dioxide formed by partially oxidizing the layerof amorphous polysilicon; a layer of silicon nitride formed on the layerof silicon dioxide; and a second layer of silicon dioxide formed on thelayer of silicon nitride, the control gate formed on the second layer ofsilicon dioxide.
 171. The composite of claim 170, wherein the layer ofsilicon dioxide is formed by chemical vapor deposition and the secondlayer of silicon dioxide is formed by oxidation.
 172. The composite ofclaim 170, wherein the layer of amorphous polysilicon is thin.
 173. Adielectric composite for insulating a floating gate from a control gate,the composite comprising: a layer of amorphous polysilicon formed on thefloating gate; a layer of silicon dioxide formed by oxidizing the layerof amorphous polysilicon; a layer of silicon nitride formed on the layerof silicon dioxide; a layer of silicon rich nitride formed on the layerof silicon nitride; and a second layer of silicon dioxide formed on thelayer of silicon rich nitride, the control gate formed on the secondlayer of silicon dioxide.
 174. The composite of claim 173, wherein thelayer of silicon dioxide and the second layer of silicon dioxide areformed by chemical vapor deposition.
 175. The composite of claim 173,wherein the layer of amorphous polysilicon and the layer of silicon richnitride are thin.
 176. A dielectric composite for insulating a floatinggate from a control gate, the composite comprising: a layer of amorphouspolysilicon formed on the floating gate; a layer of silicon dioxideformed by partially oxidizing the layer of amorphous polysilicon; alayer of silicon nitride formed on the layer of silicon dioxide; a layerof silicon rich nitride formed on the layer of silicon nitride; and asecond layer of silicon dioxide formed on the layer of silicon richnitride, the control gate formed on the second layer of silicon dioxide.177. The composite of claim 176, wherein the layer of silicon dioxideand the second layer of silicon dioxide are formed by chemical vapordeposition.
 178. The composite of claim 176, wherein the layer ofamorphous polysilicon and the layer of silicon rich nitride are thin.179. A process for forming a dielectric composite for insulating afloating gate from a control gate, the process comprising: depositing alayer of amorphous polysilicon on the floating gate; forming a layer ofsilicon dioxide by oxidizing the layer of amorphous polysilicon;depositing a layer of silicon nitride on the layer of silicon dioxide;and forming a second layer of silicon dioxide by oxidizing the layer ofsilicon nitride, the control gate formed on the second layer of silicondioxide.
 180. The process of claim 179, wherein depositing a layer ofamorphous polysilicon results in a thin layer of amorphous polysilicon.181. The process of claim 179, wherein after forming the floating gateby flowing silane and phosphine, the deposition of the layer ofamorphous polysilicon is accomplished by reducing the flow of phosphine.182. The process of claim 181, wherein the flow of phosphine is reducedto zero.
 183. A process for forming a dielectric composite forinsulating a floating gate from a control gate, the process comprising:depositing a layer of amorphous polysilicon on the floating gate;forming a layer of silicon dioxide by partially oxidizing the layer ofamorphous polysilicon; depositing a layer of silicon nitride on thelayer of silicon dioxide; and forming a second layer of silicon dioxideby oxidizing the layer of silicon nitride, the control gate formed onthe second layer of silicon dioxide.
 184. The process of claim 183,wherein depositing a layer of amorphous polysilicon results in a thinlayer of amorphous polysilicon.
 185. The process of claim 183, whereinafter forming the floating gate by flowing silane and phosphine, thedeposition of the layer of amorphous polysilicon is accomplished byreducing the flow of phosphine.
 186. The process of claim 185, whereinthe flow of phosphine is reduced to zero.
 187. A process for forming adielectric composite for insulating a floating gate from a control gate,the process comprising: depositing a layer of amorphous polysilicon onthe floating gate; forming a layer of silicon dioxide by oxidizing thelayer of amorphous polysilicon; depositing a layer of silicon nitride onthe layer of silicon dioxide; depositing a layer of silicon rich nitrideon the layer of silicon nitride; and forming a second layer of silicondioxide by oxidizing the layer of silicon rich nitride, the control gateformed on the second layer of silicon dioxide.
 188. The process of claim187, wherein depositing of the layer of amorphous polysilicon results ina thin layer of amorphous polysilicon, and depositing a layer of siliconrich nitride results in a thin layer of silicon rich nitride.
 189. Theprocess of claim 187, wherein after forming the floating gate by flowingsilane and phosphine, the deposition of the layer of amorphouspolysilicon is accomplished by reducing the flow of phosphine.
 190. Theprocess of claim 189, wherein the flow of phosphine is reduced to zero.191. The process of claim 187, wherein after depositing a layer ofsilicon nitride by flowing dichlorosilane and ammonia, the deposition ofthe layer of silicon rich nitride is accomplished by reducing the flowof ammonia.
 192. The process of claim 191, wherein the flow of ammoniais reduced to zero.
 193. The process of claim 187, wherein after formingthe floating gate by flowing silane and phosphine, the deposition of thelayer of amorphous polysilicon is accomplished by reducing the flow ofphosphine, and after depositing the layer of silicon nitride by flowingdichlorosilane and ammonia, the deposition of the silicon rich nitridelayer is accomplished by reducing the flow of ammonia.
 194. The processof claim 193, wherein the flow of phosphine is reduced to zero, and theflow of ammonia is reduced to zero.
 195. The process of claim 187,wherein after depositing a layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 196. Theprocess of claim 195, wherein the flow of ammonia is reduced to zero.197. The process of claim 187, wherein after forming the floating gateby flowing silane and phosphine, the deposition of the layer ofamorphous polysilicon is accomplished by reducing the flow of phosphine,and after depositing the layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 198. Theprocess of claim 197, wherein the flow of phosphine is reduced to zero,and the flow of ammonia is reduced to zero.
 199. A process for forming adielectric composite for insulating a floating gate from a control gate,the process comprising: depositing a layer of amorphous polysilicon onthe floating gate; forming a layer of silicon dioxide by partiallyoxidizing the layer of amorphous polysilicon; depositing a layer ofsilicon nitride on the layer of silicon dioxide; depositing a layer ofsilicon rich nitride on the layer of silicon nitride; and forming asecond layer of silicon dioxide by oxidizing the layer of silicon richnitride, the control gate formed on the second layer of silicon dioxide.200. The process of claim 199, wherein depositing of the layer ofamorphous polysilicon results in a thin layer of amorphous polysilicon,and depositing a layer of silicon rich nitride results in a thin layerof silicon rich nitride.
 201. The process of claim 199, wherein afterforming the floating gate by flowing silane and phosphine, thedeposition of the layer of amorphous polysilicon is accomplished byreducing the flow of phosphine.
 202. The process of claim 201, whereinthe flow of phosphine is reduced to zero.
 203. The process of claim 199,wherein after depositing a layer of silicon nitride by flowingdichlorosilane and ammonia, the deposition of the layer of silicon richnitride is accomplished by reducing the flow of ammonia.
 204. Theprocess of claim 203, wherein the flow of ammonia is reduced to zero.205. The process of claim 199, wherein after forming the floating gateby flowing silane and phosphine, the deposition of the layer ofamorphous polysilicon is accomplished by reducing the flow of phosphine,and after depositing the layer of silicon nitride by flowingdichlorosilane and ammonia, the deposition of the silicon rich nitridelayer is accomplished by reducing the flow of ammonia.
 206. The processof claim 205, wherein the flow of phosphine is reduced to zero, and theflow of ammonia is reduced to zero.
 207. The process of claim 199,wherein after depositing a layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 208. Theprocess of claim 207, wherein the flow of ammonia is reduced to zero.209. The process of claim 199, wherein after forming the floating gateby flowing silane and phosphine, the deposition of the layer ofamorphous polysilicon is accomplished by reducing the flow of phosphine,and after depositing the layer of silicon nitride by flowingtetrachlorosilane and ammonia, the deposition of the silicon richnitride layer is accomplished by reducing the flow of ammonia.
 210. Theprocess of claim 209, wherein the flow of phosphine is reduced to zero,and the flow of ammonia is reduced to zero.
 211. A nonvolatile memorycell comprising: a substrate; a source and drain formed on thesubstrate; an insulator formed on the source and drain; a floating gateformed on the insulator; a composite formed on the floating gate, thecomposite comprising: a layer of amorphous polysilicon formed on thefloating gate; a layer of silicon dioxide formed on the layer ofamorphous polysilicon; a layer of silicon nitride formed on the layer ofsilicon dioxide; and a second layer of silicon dioxide formed on thesilicon rich nitride; and a control gate formed on the composite. 212.The nonvolatile memory cell of claim 211, wherein the insulator is atunnel oxide.
 213. The nonvolatile memory cell of claim 211, wherein thelayer of amorphous polysilicon formed on the floating gate is thin. 214.A nonvolatile memory cell comprising: a substrate; a source and drainformed on the substrate; an insulator formed on the source and drain; afloating gate formed on the insulator; a composite formed on thefloating gate, the composite comprising: a layer of amorphouspolysilicon formed on the floating gate; a layer of silicon dioxideformed on the layer of amorphous polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the silicon rich nitride; and a control gate formed onthe composite.
 215. The nonvolatile memory cell of claim 214, whereinthe insulator is a tunnel oxide.
 216. The nonvolatile memory cell ofclaim 214, wherein the layer of amorphous polysilicon formed on thefloating gate is thin.
 217. The nonvolatile memory cell of claim 214,wherein the layer of silicon rich nitride formed on the layer of siliconnitride is thin.
 218. The nonvolatile memory cell of claim 214, whereinthe layer of amorphous polysilicon formed on the floating gate is thinand the layer of silicon rich nitride formed on the layer of siliconnitride is thin.
 219. A memory device, comprising: a plurality of memorycells, at least one of the memory cells comprising: a substrate; asource and drain formed on the substrate; an insulator formed on thesource and drain; a floating gate formed on the insulator; a compositeformed on the floating gate, the composite comprising: a layer ofamorphous polysilicon formed on the floating gate; a layer of silicondioxide formed on the layer of amorphous polysilicon; a layer of siliconnitride formed on the layer of silicon dioxide; and a second layer ofsilicon dioxide formed on the silicon rich nitride; and a control gateformed on the composite; addressing circuity coupled to the plurality ofmemory cells for accessing at least one of the memory cells; and a readcircuit coupled to the plurality of memory cells for reading data fromat least one of the memory cells.
 220. The memory device of claim 219,wherein the insulator is a tunnel oxide.
 221. The memory device of claim219, wherein the layer of amorphous polysilicon formed on the floatinggate is thin.
 222. A memory device, comprising: a plurality of memorycells, at least one of the memory cells comprising: a substrate; asource and drain formed on the substrate; an insulator formed on thesource and drain; a floating gate formed on the insulator; a compositeformed on the floating gate, the composite comprising: a layer ofamorphous polysilicon formed on the floating gate; a layer of silicondioxide formed on the layer of amorphous polysilicon; a layer of siliconnitride formed on the layer of silicon dioxide; a layer of silicon richnitride formed on the layer of silicon nitride; and a second layer ofsilicon dioxide formed on the silicon rich nitride; and a control gateformed on the composite; addressing circuity coupled to the plurality ofmemory cells for accessing at least one of the memory cells; and a readcircuit coupled to the plurality of memory cells for reading data fromat least one of the memory cells.
 223. The memory device of claim 222,wherein the insulator is a tunnel oxide.
 224. The memory device of claim222, wherein the layer of amorphous polysilicon formed on the floatinggate is thin.
 225. The memory device of claim 222, wherein the layer ofsilicon rich nitride formed on the layer of silicon nitride is thin.226. The memory device of claim 222, wherein the layer of amorphouspolysilicon formed on the floating gate is thin and the layer of siliconrich nitride formed on the layer of silicon nitride is thin.
 227. Asystem comprising: a processor; and a memory device coupled to theprocessor, the memory device comprising: a plurality of memory cells, atleast one of the memory cells comprising: a substrate; a source anddrain formed on the substrate; an insulator formed on the source anddrain; a floating gate formed on the insulator; a composite formed onthe floating gate, the composite comprising: a layer of amorphouspolysilicon formed on the floating gate; a layer of silicon dioxideformed on the layer of amorphous polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; and a second layer of silicondioxide formed on the silicon rich nitride; and a control gate formed onthe composite; addressing circuity coupled to the plurality of memorycells for accessing at least one of the memory cells; and a read circuitcoupled to the plurality of memory cells for reading data from at leastone of the memory cells.
 228. The system of claim 227, wherein theinsulator is a tunnel oxide.
 229. The system of claim 227, wherein thelayer of amorphous polysilicon formed on the floating gate is thin. 230.A system comprising: a processor; and a memory device coupled to theprocessor, the memory device comprising: a plurality of memory cells, atleast one of the memory cells comprising: a substrate; a source anddrain formed on the substrate; an insulator formed on the source anddrain; a floating gate formed on the insulator; a composite formed onthe floating gate, the composite comprising: a layer of amorphouspolysilicon formed on the floating gate; a layer of silicon dioxideformed on the layer of amorphous polysilicon; a layer of silicon nitrideformed on the layer of silicon dioxide; a layer of silicon rich nitrideformed on the layer of silicon nitride; and a second layer of silicondioxide formed on the silicon rich nitride; and a control gate formed onthe composite; addressing circuity coupled to the plurality of memorycells for accessing at least one of the memory cells; and a read circuitcoupled to the plurality of memory cells for reading data from at leastone of the memory cells.
 231. The system of claim 230, wherein theinsulator is a tunnel oxide.
 232. The system of claim 230, wherein thelayer of amorphous polysilicon formed on the floating gate is thin. 233.The system of claim 230, wherein the layer of silicon rich nitrideformed on the layer of silicon nitride is thin.
 234. The system of claim230, wherein the layer of amorphous polysilicon formed on the floatinggate is thin and the layer of silicon rich nitride formed on the layerof silicon nitride is thin.